M66852J datasheet(1/15 Pages) MITSUBISHI

Part #	M66852J

Description	SRAM TYPE FIFO MEMORY

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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SRAM TYPE FIFO MEMORY

M66850J/FP, M66851J/FP

M66852J/FP, M66853J/FP

MITSUBISHI <DIGITAL ASSP>

PIN CONFIGURATION (TOP VIEW)

DESCRIPTION

M66850/851/852/853 are very high-speed and clock synchronous

FIFO(First-In,First-Out) memories fabricated by high-speed CMOS

technology.

These FIFOs are applicable for a data buffer as networks and

communications.

The write operation is controlled by a write clock pin(WCLK) and

two write enable pins(WEN1,WEN2).

Data present at the data input pins(D0-D8) is written into the

Synchronous FIFO on every rising write clock edge when the

device is enabled for writing.

The read operation is controlled by a read clock pin(RCLK) and

two read enable pins(REN1,REN2).

Data is read from the Synchronous FIFO on every rising read clock

edge when the device is enabled for reading. An output enable

pin(OE) controls the states of the data output pins(Q0-Q8).

MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty

flag EF and the full flag FF are fixed flags. The almost empty flag

PAE and the almost full flag PAF are programmable flags. The

programmable flag offset is initiated by the load pin(LD).

FEATURES

• Memory configuration

64words x 9bits (M66850J/FP)

256words x 9bits (M66851J/FP)

512words x 9bits (M66852J/FP)

1024words x 9bits (M66853J/FP)

• Write and Read Clocks can be independent

• Advanced CMOS technology

• Programmable Almost-Empty and Almost-Full flags

• High-speed : 25ns cycle time

• Package Available :

32-pin Pastic Leaded Chip Carrier(PLCC)

32-pin Low profile Quad Flat Package(LQFP)

APPLICATION

• Data Buffer for networks communications.

Outline 32P0(M66850 – 853J)

29

13

28

27

26

25

24

23

22

21

5

6

7

8

9

10

11

12

D1

D0

PAF

PAE

GND

REN1

RCLK

REN2

OE

RS

WEN1

WCLK

WEN2/LD

VCC

Q8

Q7

Q6

Q5

Outline 32P6B(M66850 – 853FP)

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

D1

D0

PAF

PAE

GND

REN1

RCLK

REN2

WEN1

WCLK

WEN2/LD

VCC

Q8

Q7

Q6

Q5

BLOCK DIAGRAM

RESET

LOGIC

WRITE

CONTROL

WRITE

POINTER

INPUT

REGISTER

OUTPUT

REGISTER

READ

POINTER

READ

CONTROL

OFFSET

REGISTER

FLAG

LOGIC

WCLK

Q0-Q8

RCLK

WEN1

WEN2

RS

OE

REN1

REN2

EF

PAE

FF

PAF

LD

MEMORY

ARRAY

D0-D8

1

–

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