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HDD64M72D18W-10A Datasheet(PDF) 7 Page - Hanbit Electronics Co.,Ltd |
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HDD64M72D18W-10A Datasheet(HTML) 7 Page - Hanbit Electronics Co.,Ltd |
7 / 12 page HANBit HDD64M72D18W URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd . REV 1.0 (August.2002) Active standby current IDD3N CS# >= VIH(min), CKE>=VIH(min) one bank active, active – precharge, tRC=tRASmax tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, DQ, DQS and DM inputs changing twice per clock cycle Address and other control inputs changing once per clock cycle 1053 900 900 mA Operating current (burst read) IDD4R BL = 2, reads, continuous burst One bank open, Address and control inputs changing once per clock cycle, IOUT = 0mA 1620 1845 1845 mA Operating current (Bust write) IDD4W BL = 2, write, continuous burst One bank open, Address and control inputs changing once per clock cycle 1485 1755 1755 mA Auto refresh current IDD5 tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz, distributed refresh 1845 2070 2070 mA Normal 54 54 54 Self refresh current Low Power IDD6 CKE =< 0.2V, External clock should be on tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B 27 27 27 mA Operating current (Four bank operation) IDD7A Four bank interleaving with BL=4 -Refer to the following page for detailed test condition 2790 3015 3015 mA Notes: Operation at above absolute maximum rating can adversely affect device reliability AC OPERATING CONDITIONS PARAMETER STMBOL MIN MAX UNIT NOTE Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.31 3 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC) VREF - 0.31 V 3 Input Differential Voltage, CK and CK inputs VID (AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX (AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS PARAMETER VALUE UNIT NOTE Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 1.0 V Input Levels(VIH/VIL) VREF+0.35/VREF V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit V |
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