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HDD64M72D18RW-13B Datasheet(PDF) 6 Page - Hanbit Electronics Co.,Ltd |
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HDD64M72D18RW-13B Datasheet(HTML) 6 Page - Hanbit Electronics Co.,Ltd |
6 / 12 page HANBit HDD64M72D18RPW URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd. REV 1.0 (August.2002) CAPACITANCE (VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25°C, f = 100MHz) DESCRIPTION SYMBOL MIN MAX UNITS Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE) CIN1 - 12 pF Input capacitance(CKE0,CKE1) CIN2 - 12 pF Input capacitance(/CS0,/CS1) CIN3 - 11 pF Input capacitance(CK0~/CK1) CIN4 - 12 pF Input capacitance(DM0~DM8) CIN5 - 16 pF Data & DQS input/output capacitance (DQ0 ~ DQ63, DQS0~DQS8) COUT1 - 16 pF Data input/output capacitance (CB0~CB7)) COUT2 - 16 pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25°C) version pARAMETER Symbo l TEST Condition -10A -13A -13B Unit Operating current (One bank active-Precharge) IDD0 tRC ≥ tRC(min), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B DQ,DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle 1515 1695 1695 mA Operating current (One bankOperation) IDD1 One bank open, BL=4,Reads-Refer to the following page for detailed test condition 1605 1875 1875 mA Precharge power- down standby current IDD2P All banks idle, power-down mode CKE ≤ VIL(max), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B VIN = VREF for DQ,DQS and DM 885 1020 1020 mA Precharge Floating standby current IDD2F /CS ≥ VIH(min), All banks idle CKE ≥ VIH(min), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B Address and control inputs changing once per clock cycle VIN = VREF for DQ,DQS and DM 1020 1155 1155 mA Precharge Quiet Standby current IDD2Q /CS ≥ VIH(min), All banks idle CKE ≥ VIH(min), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B Address and other control inputs stable with keeping ≥ V IH(min) or ≤ V IL(max) VIN = VREF for DQ,DQS and DM 975 1110 1110 Active power-down Mode standby current IDD3P One bank active; power-down mode; CKE ≤ VIL(max), tCK=100MHz for DDR200,133MHz for DDR266A & DDR266B VIN = VREF for DQ,DQS and DM. 1020 1155 1155 mA Active standby current IDD3N CS# >= VIH(min), CKE>=VIH(min) one bank active, active – precharge, tRC=tRASmax tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, DQ, DQS and DM inputs changing twice per clock cycle Address and other control inputs changing once per clock cycle 1110 1290 1290 mA |
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