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LM98555CCMH Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LM98555CCMH Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 9 page Application Information The LM98555 is a fully integrated clock driver/buffer for high speed CCD applications. It provides high performance low impedance drivers, with optimized low skew performance of the P1 and P2 outputs. Enable inputs allow use of two, four, six, or all eight P1 and P2 drivers to optimize the amount of drive for the application. The 64 pin thermally enhanced TSSOP provides excellent power handling through the use of an exposed heat transfer pad on the underside of the package. THERMAL GUIDELINES The LM98555’s maximum power dissipation limit, shown in the Operating Conditions section, must be strictly adhered to. The product’s multiple high-strength drivers, with their ability to drive a wide-range of loads, make it possible to be within spec on each output and yet violate the aggregate maximum power dissipation limit for the total product. Spe- cial caution must be paid to this by limiting the chip’s oper- ating conditions (loads, power supply, number of parallel drivers enabled, frequency of operation) to make certain that the maximum power dissipation limit is never exceeded. Thermal characterization of the device has been done to provide reference points under specific conditions. θ junction to ambient was measured using a 5.5 inch by 3 inch, 4 layer PCB. The thermal contact pad on the board was connected using vias to a full ground plane on one of the internal layers. The recommended thermal pad is shown in Figure 4. The vias shown provide a path for heat to flow from the pad to a heat sinking or dissipating area of the printed circuit board. The following figures show several typical examples of how this can be done, and illustrate how heat is conducted away from the IC to larger areas where it is dissipated. In multi-layer board applications, one or more internal planes are usually dedicated as a ground plane. Connecting the thermal pad to this ground plane with vias will usually pro- vide adequate heat management. In 2 layer boards, it is 20126406 FIGURE 4. Exposed Pad Land Pattern 20126407 FIGURE 5. 4 Layer PCB - Example 1 20126409 FIGURE 6. 4 Layer PCB - Example 2 20126408 FIGURE 7. 2 Layer PCB www.national.com 7 |
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