HANBit

HSD8M64F8V/VA

URL:www.hbe.co.kr

- 8 -

HANBit Electronics Co.,Ltd.

REV.1.0(August.2002)

Auto

precharge

disable

L

Column

Address

(A0 ~ A9)

4

Write &

column

address

Auto

precharge

disable

H

X

L

H

L

L

X

V

H

4,5

Burst Stop

H

X

L

L

H

L

X

X

6

Bank selection

V

L

Precharg

e

All banks

H

X

L

L

H

L

X

X

H

X

H

X

X

X

Entry

H

L

L

V

V

V

X

Clock suspend or

active power down

Exit

L

H

X

X

X

X

X

X

H

X

X

X

Entry

H

L

L

H

H

H

X

H

X

X

X

Precharge

power

down mode

Exit

L

H

L

V

V

V

X

X

DQM

H

X

V

X

7

H

X

X

X

No operation command

H

X

L

H

H

H

X

X

(V=Valid, X=Don't care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

TIMING DIAGRAMS

Please refer to attached timing diagram chart (II)