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MB84VD2108XEM-70 Datasheet(PDF) 5 Page - SPANSION |
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MB84VD2108XEM-70 Datasheet(HTML) 5 Page - SPANSION |
5 / 53 page MB84VD2108XEM/2109XEM-70 4 s PIN DESCRIPTION Pin Name Function Input/Output A16 to A0 Address Inputs (Common) I A19 to A17, A-1 Address Input (Flash) I SA Address Input (SRAM) I DQ15 to DQ0 Data Inputs / Outputs (Common) I/O CEf Chip Enable (Flash) I CE1s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I RY/BY Ready/Busy Outputs (Flash) Open Drain Output O UB Upper Byte Control (SRAM) I LB Lower Byte Control (SRAM) I CIOf I/O Configuration (Flash) CIOf =VCCf is Word mode ( ×16 ), CIOf =VSS is Byte mode ( × 8 ) I CIOs I/O Configuration (SRAM) CIOs =VCCs is Word mode (×16), CIOs =VSS is Byte mode (× 8) I RESET Hardware Reset Pin / Sector Protection Un- lock (Flash) I WP/ACC Write Protect / Acceleration (Flash) I N.C. No Internal Connection — VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power |
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