K6R4016V1C-C/C-L, K6R4016V1C-I/C-P

CMOS SRAM

PRELIMPreliminaryPPPPPPPPPINARY

Rev 5.0

- 8 -

September 2001

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE

to the end of write.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not . be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

Address

CS

Valid Data

UB, LB

WE

Data in

Data out

High-Z

High-Z(8)

High-Z

Address

CS

Valid Data

WE

Data in

Data out

High-Z

High-Z(8)

UB, LB

High-Z

High-Z