GS881Z18/32/36B(T/D)-xxxV

Rev: 1.00 6/2006

31/37

© 2006, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Timing Diagram

tTH

tTS

tTKQ

tTH

tTS

tTH

tTS

tTKL

tTKL

tTKH

tTKH

tTKC

tTKC

TCK

TDI

TMS

TDO

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

TCK Cycle Time

tTKC

50

—

ns

TCK Low to TDO Valid

tTKQ

—

20

ns

TCK High Pulse Width

tTKH

20

—

ns

TCK Low Pulse Width

tTKL

20

—

ns

TDI & TMS Set Up Time

tTS

10

—

ns

TDI & TMS Hold Time

tTH

10

—

ns

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.