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GS882Z36BB-150IV Datasheet(PDF) 1 Page - GSI Technology |
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GS882Z36BB-150IV Datasheet(HTML) 1 Page - GSI Technology |
1 / 33 page Rev: 1.04 6/2006 1/33 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. GS882Z18/36B(B/D)-xxxV 9Mb Pipelined and Flow Through Synchronous NBT SRAM 250 MHz–150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O 119-bump and 165-bump BGA Commercial Temp Industrial Temp Features • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • On-chip parity encoding and error detection • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 18M devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down • JEDEC-standard 119-bump BGA and 165-bump FPBGA packages • RoHS-compliant 119-bump and 165-bump BGA packages available Functional Description The GS882Z18/36B(B/D)-xxxV is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GGS882Z18/36B(B/D)-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising- edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS882Z18/36B(B/D)-xxxV is implemented with GSI's high performance CMOS technology and is available in JEDEC-standard 119-bump BGA and 165-bump FPBGA packages. Paramter Synopsis -250 -200 -150 Unit Pipeline 3-1-1-1 tKQ tCycle 3.0 4.0 3.0 5.0 3.8 6.7 ns ns Curr (x18) Curr (x32/x36) 195 220 165 185 140 160 mA mA Flow Through 2-1-1-1 tKQ tCycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 155 175 140 155 128 145 mA mA |
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