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GS8170DD36C-333I Datasheet(PDF) 8 Page - GSI Technology |
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GS8170DD36C-333I Datasheet(HTML) 8 Page - GSI Technology |
8 / 29 page GS8170DD36C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 8/29 © 2002, GSI Technology, Inc. Burst Order The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have been accessed. SigmaRAMs always count in linear burst order. Notes: 1. The burst counter wraps to initial state on the 3rd rising edge of clock. 2. The DDR SigmaRAM always begins an read or write at A0 = 0. A0 is internally set to 0 at the rising edge of clock and is not available to the user. Echo Clock ΣRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2). It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks. Programmable Enables ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at VDD, E2 functions as an active high enable. If EP2 is held to VSS, E2 functions as an active low chip enable input. Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four SRAMs can be made to look like one larger RAM to the system. Linear Burst Order A[1:0] 1st address (Rising Edge CK) 00 10 2nd address (Falling Edge CK) 01 11 3rd address (Rising Edge CK) 10 00 4th address (Falling Edge CK) 11 01 |
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