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GS8170DD36C-200I Datasheet(PDF) 4 Page - GSI Technology |
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GS8170DD36C-200I Datasheet(HTML) 4 Page - GSI Technology |
4 / 29 page GS8170DD36C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 4/29 © 2002, GSI Technology, Inc. Read Operations Double Data Rate Read In applications where a data rate markedly faster than the RAM’s latency is desired, the Double Data Rate protocol doubles the data transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In Double Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The output register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to the next falling edge of clock as well. SigmaRAM DDR RAMs burst in linear order only. Write Operations Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low. Double Data Rate Write A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address and command. Double Data Rate Pipelined Read QA0 QA1 QC0 QC1 QD0 QD1 CK Read Deselect AXX F Read Read Read ADV DE C /E1 /W DQ Address CQ Key Hi-Z Access |
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