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GS8170DW36AGC-350 Datasheet(PDF) 7 Page - GSI Technology |
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GS8170DW36AGC-350 Datasheet(HTML) 7 Page - GSI Technology |
7 / 32 page GS8170DW36/72AC-350/333/300/250 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 4/2005 7/32 © 2003, GSI Technology Two Byte Write Control Example with Double Late Write SigmaRAM Special Functions Burst Cycles Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. DA DB DE DA DC /BB DQA0-DQA8 DQB0-DQB8 CQ /E1 ADV /BA D C Address A B ADV CK Write Write F E Write Non-Write Write |
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