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GS8662Q18E-167 Datasheet(PDF) 7 Page - GSI Technology |
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GS8662Q18E-167 Datasheet(HTML) 7 Page - GSI Technology |
7 / 35 page Preliminary GS8662Q08/09/18/36E-300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01 9/2005 7/35 © 2005, GSI Technology Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half. Alternating Read-Write Operations SigmaQuad-II SRAMs follow a few simple rules of operation. - Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port. - Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM. - All address, data, and control inputs are sampled on clock edges. In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details. SigmaQuad-II B2 SRAM DDR Read The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle. SigmaQuad-II B2 Double Data Rate SRAM Read First Read A NOP Write B Read C Write D Read E Write F Read G Write H A B C D E F G H B B+1 D D+1 F F+1 H H+1 B B+1 D D+1 F F+1 H H+1 A A+1 C C+1 E K K Address R W BWx D C C Q CQ CQ |
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