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GS82032AT-66 Datasheet(PDF) 1 Page - GSI Technology |
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GS82032AT-66 Datasheet(HTML) 1 Page - GSI Technology |
1 / 22 page GS82032AT-180/166/150/133/100/66/4/5/6 64K x 32 2Mb Synchronous Burst SRAM 180 MHz–66 MHz 3.3 V VDD 3.3 V and 2.5 V I/O TQFP Commercial Temp Industrial Temp Rev: 1.12 10/2004 1/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Features • FT pin for user-configurable flow through or pipelined opera- tion • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC standard 100-lead TQFP package • Pb-Free 100-lead TQFP package available Functional Description Applications The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output Register can be controlled by the user via the FT mode pin (Pin 14 in the TQFP). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS82032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. Parameter Synopsis -180 -166 -150 -133 (-4) -100 (-5) -66 (-6) Pipeline 3-1-1-1 tCycle tKQ IDD 5.5 ns 3.2 ns 155 mA 6 ns 3.5 ns 140 mA 6.6 ns 3.8 ns 130 mA 7.5 ns 4 ns 115 mA 10 ns 5 ns 90 mA 12.5 ns 6 ns 65 mA Flow Through 2-1-1-1 tCycle tKQ IDD 9.1 ns 8 ns 100 mA 10 ns 8.5 ns 90 mA 10.5 ns 9 ns 85 mA 12 ns 10 ns 80 mA 15 ns 12 ns 65 mA 20 ns 18 ns 50 mA |
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Similar Description - GS82032AT-66 |
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