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AD7453BRT-REEL7 Datasheet(PDF) 4 Page - Analog Devices

Part # AD7453BRT-REEL7
Description  Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7453BRT-REEL7 Datasheet(HTML) 4 Page - Analog Devices

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REV. 0
–4–
AD7453
TIMING SPECIFICATIONS1, 2
(VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX,
unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
3
10
kHz min
10
MHz max
tCONVERT
16
¥ tSCLK
tSCLK = 1/fSCLK
1.6
ms max
tQUIET
60
ns min
Minimum Quiet Time between the End of a Serial Read and the Next Falling
Edge of
CS
t1
10
ns min
Minimum
CS Pulse Width
t2
10
ns min
CS Falling Edge to SCLK Falling Edge Setup Time
t3
4
20
ns max
Delay from
CS Falling Edge Until SDATA Three-State Disabled
t4
4
40
ns max
Data Access Time After SCLK Falling Edge
t5
0.4 tSCLK
ns min
SCLK High Pulse Width
t6
0.4 tSCLK
ns min
SCLK Low Pulse Width
t7
10
ns min
SCLK Edge to Data Valid Hold Time
t8
5
10
ns min
SCLK Falling Edge to SDATA Three-State Enabled
35
ns max
SCLK Falling Edge to SDATA Three-State Enabled
tPOWER-UP
6
1
ms max
Power-Up Time from Full Power-Down
NOTES
1Sample tested at 25
∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2See Figure 1 and the Serial Interface section.
3Mark/Space ratio for the SCLK input is 40/60 to 60/40.
4Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD = 5 V and time for an output to cross
0.4 V or 2.0 V for VDD = 3 V.
5t
8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6See Power-Up Time section.
Specifications subject to change without notice.
CS
SCLK
SDATA
t2
t3
t4
t7
t6
t8
tQUIET
t5
tCONVERT
12
345
13
14
15
16
00
0
DB11
DB10
DB2
DB1
DB0
THREE-STATE
4 LEADING ZEROS
0
t1
B
Figure 1. AD7453 Serial Interface Timing Diagram


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