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AD9879BS Datasheet(PDF) 11 Page - Analog Devices

Part # AD9879BS
Description  Mixed-Signal Front End Set-Top Box, Cable Modem
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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REV. 0
AD9879
–11–
Bit 5: Rx Port Fast Edge Rate
Setting this bit to 1 increases the output drive strength of all
digital output pins, except MCLK, REFCLK, - _OUT, and
FLAG1. These pins always have high output drive capability.
Bit 7: ADC Clocked Direct from OSCIN
When set high, the input clock at OSCIN is used directly as the
ADC sampling clock. When set low, the internally generated
master clock, MCLK, is divided by two and used as the ADC
sampling clock. Best ADC performance is achieved when the
ADCs are sampled directly from fOSCIN using an external crystal
or low jitter crystal oscillator.
Register C—DIE REVISION
Bits 0 to 3: Version
The die version of the chip can be read from this register.
Register D—Tx Frequency Tuning Words LSBs
This register accommodates two least significant bits for both of
the frequency tuning words. See description of Carrier Frequency
Tuning.
Register E—DAC Gain Control
Bits 0 to 3: DAC Fine Gain Control
This bit field sets the DAC gain if the Tx Path AD8321/AD8323
Gain Control Select bit (Register F, Bit 3) is set to 0. The DAC
gain can be set from 0.0 dB to 7.5 dB in increments of 0.5 dB.
Table III details the programming.
Table III.
Bits [3:0]
DAC Gain
0000
0.0 dB (Default)
0001
0.5 dB
0010
1.0 dB
0011
1.5 dB
....
....
1110
7.0 dB
1111
7.5 dB
Register F — Tx PATH CONFIGURATION
Bit 0: Tx Path Transmit Single Tone
Active high configures the AD9879 for single-tone applications
(e.g., FSK). The AD9879 will supply a single frequency output
as determined by the frequency tuning word selected by the
active profile. In this mode, the TXIQ input data pins are ignored
but should be tied to a valid logic voltage level. Default value is
0 (inactive).
Bit 1: Tx Path Spectral Inversion
When set to 1, inverted modulation is performed:
MODULAR_OUT
I cos
t
Q sin
t
=
() +
()
[]
ww
Default is logic zero, noninverted modulation:
MODULAR_OUT
I cos
t
Q sin
t
=
() +
()
[]
ww
Bit 2: Tx Path Bypass Sinc
–1 Filter
Setting this bit high bypasses the digital inverse sinc filter of the
Tx path.
Bit 3: Tx Path AD8322/AD8327 Gain Control Mode
This bit changes the manner in which transmit gain control is
performed. Typically either AD8321/AD8323 (default 0) or
AD8222/AD8327 (default 1) variable gain cable drivers are
programmed over the chip’s 3-wire CA interface. The Tx gain
control select changes the interpretation of the bits in Registers
13 and 17. See Cable Driver Gain Control.
Bit 5: Tx Path Select Profile 1
The AD9879 quadrature digital upconverter is capable of stor-
ing two preconfigured modulation modes called profiles.
Each profile defines a transmit frequency tuning word and cable
driver amplifier gain (/DAC gain) setting. The Profile Select bit
or PROFILE pin programs the current register profile to be used.
The Profile Select bit should always be “0” if the PROFILE pin
is to be used to switch between profiles. Using the Profile Select
bit as a means of switching between different profiles requires
the PROFILE pin to be tied low.
Registers 10–17: Carrier Frequency Tuning
Tx Path Frequency Tuning Words
The frequency tuning word (FTW) determines the DDS-generated
carrier frequency (fC) and is formed via a concatenation of
register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB and Bit 0 is the LSB.
The carrier frequency equation is given as:
f
FTW
f
C
SYSCLK
[]/226
where fM
f
and FTW
SYSCLK
OSCIN
< ¥
0
2000000
Changes to FTW bytes take effect immediately.
Cable Driver Gain Control
The AD9879 has a 3-pin interface to the AD832x family of
programmable gain cable driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9879.
In its Default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register F is set high, Bits [7:4] determine the 8-bit
word sent over the CA interface according to Table IV.
Table IV.
Bits [7:4]
CA Interface Transmit Word
0000
0000 0000 (Default)
0001
0000 0001
...
...
0111
0100 0000
1000
1000 0000
In this mode, the lower bits determine the fine gain setting
of the DAC output.
Table V.
Bits [3:0]
DAC Fine Gain
0000
0.0 dB (Default)
0001
0.5 dB
...
...
1110
7.0 dB
1111
7.5 dB
New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
value is 0x00 (lowest gain).


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