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74ALS253DB Datasheet(PDF) 2 Page - NXP Semiconductors |
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74ALS253DB Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 9 page Philips Semiconductors Product specification 74ALS253 Dual 4-input multiplexer (3-State) 2 1991 Feb 08 853–1378 01670 FEATURES • 3-State outputs for bus interface and multiplex operation • Common select inputs • Separate output enable inputs DESCRIPTION The 74ALS253 has two identical 4-input multiplexers with 3-State outputs which select 2 bits from four sources by using common select input (S0, S1). When the individual output enable (OEa, OEb) inputs of the 4-input multiplexers are High, the outputs are forced to a High impedance (Z) state. The 74ALS253 is the logic implementation of 2-pole, 4-position switch being determined by the logic levels supplied to the common select inputs. To avoid exceeding the maximum current ratings when the outputs of the 3-State devices are tied together, all but one device must be in the High impedance state. Therefore, only one output enable must be achieved at a time. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74ALS253 7.0ns 8mA PIN CONFIGURATION 16 15 14 13 12 11 10 7 6 5 4 3 2 1 Ya VCC I2b I1b I0b I3b OEb S0 OEa S1 I0a I3a I2a I1a 9 8 GND Yb SF00798 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 16-pin plastic DIP 74ALS253N SOT38-4 16-pin plastic SO 74ALS253D SOT109-1 16-pin plastic SSOP Type II 74ALS253DB SOT338-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW I0a – I3a Port A data inputs 1.0/1.0 20 µA/0.1mA I0b – I3b Port B data inputs 1.0/1.0 20 µA/0.1mA S0, S1 Common select inputs 1.0/1.0 20 µA/0.1mA OEa Port A Output Enable input (active-Low) 1.0/1.0 20 µA/0.1mA OEb Port B Output Enable input (active-Low) 1.0/1.0 20 µA/0.1mA Ya – Yb 3-State outputs 130/240 2.6mA/24mA NOTE: One (1.0) ALS unit load is defined as: 20 µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL 3 4 5 VCC = Pin 16 GND = Pin 8 SF00799 9 7 14 2 1 S0 S1 OEa 15 6 13 12 11 10 OEb Ya Yb I0a I1a I2a I3a I0b I1b I2b I3b IEC/IEEE SYMBOL SC00073 MUX 1 6 15 10 11 7 9 0 5 2 EN 4 3 13 12 1 3 0 G 0 3 2 14 2 |
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