TLK3104SA

QUAD 3.125 Gbps SERIAL TRANSCEIVER

SCAS651B-– AUGUST 2000 – REVISED SEPTEMBER 2001

10

POST OFFICE BOX 655303

channel clock to serial transmit clock synchronization (continued)

Channel

Logic

Protocol Device

TX

FIFO

Channel A

TCA

TLK3104SA

Serdes

Core

Data A

Channel

Logic

TX

FIFO

Channel B

TCB

Data B

Serdes

Core

Channel

Logic

TX

FIFO

Channel C

TCC

Data C

Serdes

Core

Channel

Logic

TX

FIFO

Channel D

TCD

Data D

Serdes

Core

Xtal OSC

RFCP/RFCN

Figure 7. Transmit and Reference Clock Relationship (Independent Channel Mode)

receive data bus timing

For each channel, the receiver portion of the TLK3104SA outputs the recovered deserialized data on receive

data bus TDx[0..9] on both the rising and falling edges of the receive data clock, as shown in Figure 8. Depending

on the state of PSYNC pin the receive data clock is either RCA (channel sync mode) or the individual receive

channel clocks, RCA–RCD (independent channel mode). When in the channel sync mode, RCB, RCC, and

RCD pins are held low.

tsu

th

th

tsu

Data

Data

RCA, RCB,

RCC, RCD

RDx[0...9]

Figure 8. Receive Interface Timing