TLE 4473 GV53

TLE 4473 GV52

Data Sheet

3

Rev. 1.0, 2004-07-14

Reset and Watchdog Behaviour:

The reset output RO1 is in high-state if the voltage on the delay capacitor

C

or equal

V

greater than the reset threshold

V

condition”), the delay capacitor

C

reset output RO1 is set to low.

At power-on, the charging process of

C

(1)

for the power-on reset delay time.

When the voltage at the delay capacitor has reached

V

watchdog circuit is enabled and discharges

C

If there is no rising edge observed at the watchdog input,

C

V

the current

I

If a watchdog pulse (rising edge at watchdog input WI) occurs during the discharge

period,

C

the periodical cycle starts again.

The watchdog timing is shown in Figure 2. The maximum duration between two

watchdog pulses corresponds to the minimum watchdog trigger time T

capacitances on pin D1 result in larger watchdog trigger time:

(2)

If the output voltage Q2 decreases below

V

When the voltage at this capacitor drops below

V

11 (RO2), i.e. the reset output is set to low-level. If the output voltage rises above the

reset threshold,

C

reset time, the voltage at the capacitor reaches

V

high again. The value of the power-on-reset time can be set within a wide range

depending of the capacitance of

C

t

Don

,

C

D1

V

DU1

×

I

DC1

-----------------------------

=

T

WI,tr max

0.42 ms/nF

C

D1

×

=