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Q67006-A9584 Datasheet(PDF) 4 Page - Infineon Technologies AG |
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Q67006-A9584 Datasheet(HTML) 4 Page - Infineon Technologies AG |
4 / 25 page Data Sheet 4 Rev. 2.0, 2005-03-24 TLE 6254-3 G Figure 1 Pin Configuration P-DSO-14-19 (top view) Table 1 Pin Definitions and Functions Pin No. Symbol Function 1INH Inhibit output; for controlling an external voltage regulator 2TxD Transmit data input; integrated pull-up, LOW: bus becomes dominant, HIGH: bus becomes recessive 3RxD Receive data output; integrated pull-up, LOW: bus is dominant, HIGH: bus is recessive 4NERR Error flag output; integrated pull-up, LOW: bus error (in normal operation mode), further functions see Table 2 5NSTB Not stand-by input; digital control input to select operation modes, see Figure 4 6ENT Enable transfer input; digital control input to select operation modes, see Figure 4 7WK Wake-Up input; if level of V WAKE changes the device indicates a wake-up from low power mode by switching the RxD outputs LOW and switching the INH output HIGH (in sleep mode), see Table 2 A E P 0332 3.V S D 7 6 5 4 3 2 1 IN H Tx D Rx D NE RR NS T B EN T WK 8 9 10 11 12 13 14 GN D CA NL CA N H RT L RT H V S V CC T L E 62 54 -3 G |
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