Philips Semiconductors

Product specification

74ALVT16899

2.5V/3.3V 18-bit latched transceiver with 16-bit parity

generator/checker (3-State)

1998 Jun 30

7

DC ELECTRICAL CHARACTERISTICS (3.3V

"0.3V RANGE)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = -40

°C to +85°C

UNIT

MIN

MAX

Input clamp voltage

–0.85

–1.2

V

High-level output voltage

V

High-level out ut voltage

2.0

2.3

V

0.07

0.2

Low–level output voltage

0.25

0.4

V

Low–level out ut voltage

0.3

0.5

V

0.4

0.55

0.55

V

Control pins

0.1

±1

Control ins

0.1

10

Input leakage current

4

0.1

20

µA

0.5

1

0.1

-5

Off current

0.1

±100

µA

Bus Hold current

75

130

Bus Hold current

Data inputs

–75

–140

µA

Data inputs

±500

Current into an output in the

10

125

µA

Power up/down 3-State output

OE/OE = Don’t care

33

±100

µA

3-State output High current

0.5

5

µA

3-State output Low current

0.5

–5

µA

0.05

0.1

Quiescent supply current

4.6

7.0

mA

0.06

0.1

Additional supply current per

0.04

0.4

mA

NOTES:

transition time of 100

6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

7. This is the bus hold overdrive current required to force the input to the opposite logic state.