IC42S16102-7TG datasheet(8/78 Pages) ICSI

Part #	IC42S16102-7TG

Description	512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

Download	78 Pages

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Manufacturer	ICSI [Integrated Circuit Solution Inc]

Direct Link	http://www.icsi.com.tw

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8 / 78 page

IC42S16102

8

Integrated Circuit Solution Inc.

DR042-0A 01/18/2005

AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)

I/O

50

Ω

+1.4V

50 pF

ZO= 50

Ω

Input

Output Load

2.4V

1.4V

0.4V

CLK

INPUT

OUTPUT

tCHI

tCH

tAC

tOH

tCS

tCK

tCL

2.4V

1.4V

0.4V

OPERATING FREQUENCY / LATENCY RELATIONSHIPS

Symbol Parameter

-5

-6

-7

Units

—

Clock Cycle Time

5

6

7

ns

—

Operating Frequency

200

166

143

MHz

tCAC

CAS Latency

3

cycle

tRCD

Active Command To Read/Write Command Delay Time

3

cycle

tRAC

RAS Latency (tRCD + tCAC)

6

cycle

tRC

Command Period (REF to REF / ACT to ACT)

10

cycle

tRAS

Command Period (ACT to PRE)

6

cycle

tRP

Command Period (PRE to ACT)

3

cycle

tRRD

Command Period (ACT[0] to ACT [1])

2

cycle

tCCD

Column Command Delay Time

1

cycle

(READ, READA, WRIT, WRITA)

tDPL

Input Data To Precharge Command Delay Time

2

cycle

tDAL

Input Data To Active/Refresh Command Delay Time

5

cycle

(During Auto-Precharge)

tRBD

Burst Stop Command To Output in HIGH-Z Delay Time

3

cycle

(Read)

tWBD

Burst Stop Command To Input in Invalid Delay Time

0

cycle

(Write)

tRQL

Precharge Command To Output in HIGH-Z Delay Time

3

cycle

(Read)

tWDL

Precharge Command To Input in Invalid Delay Time

0

cycle

(Write)

tPQL

Last Output To Auto-Precharge Start Time (Read)

–2

cycle

tQMD

DQM To Output Delay Time (Read)

2

cycle

tDMD

DQM To Input Delay Time (Write)

0

cycle

tMCD

Mode Register Set To Command Delay Time

2

cycle

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IC42S16102-7TG Datasheet(PDF) 8 Page - Integrated Circuit Solution Inc

IC42S16102-7TG Datasheet(HTML) 8 Page - Integrated Circuit Solution Inc

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