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IC42S32202-7BI Datasheet(PDF) 11 Page - Integrated Circuit Solution Inc |
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IC42S32202-7BI Datasheet(HTML) 11 Page - Integrated Circuit Solution Inc |
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11 / 62 page  IC42S32202/L Integrated Circuit Solution Inc. 11 DR042-0C 08/17/2004 Read to Precharge (CAS#Latency =2,3) 5 Write command (RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A7 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts, the first valid data-in element will be registered coincident with the Write command.Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with high- impedance at the end of the burst unless another command is initiated.The burst length and burst sequence are determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). CLK COMMAND READ A NOP NOP NOP NOP Activate NOP NOP Precharge DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 ADDRESS tRP Bank, Col A Bank(s) CAS# latency=2 tCK2, DQ s CAS# latency=3 tCK3, DQ s T0 T2 T1 T3 T4 T5 T6 T7 T8 Bank, Row CLK COMMAND DIN A 3 NOP WRITEA I NOP NOP NOP NOP NOP NOP NOP DIN A 0 DIN A1 DIN A 2 DQ0 - DQ3 The first data element and the write are registered on the same clock edge. Extra data is masked. don’t care T0 T2 T1 T3 T4 T5 T6 T7 T8 Burst Write Operation (Burst Length =4,CAS#Latency =2,3) A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/ PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). |
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