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IS62LV2568LL-55B Datasheet(PDF) 7 Page - Integrated Circuit Solution Inc |
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IS62LV2568LL-55B Datasheet(HTML) 7 Page - Integrated Circuit Solution Inc |
7 / 10 page Integrated Circuit Solution Inc. 7 SR025_0C IS62LV2568L IS62LV2568LL -55 -70 -100 Symbol Parameter Min. Max. Min. Max. Min. Max Unit tWC Write Cycle Time 55 70 100 ns tSCE1 CE1 to Write End 45 65 80 ns tSCE2 CE2 to Write End 45 65 80 ns tAW Address Setup Time to Write End 45 65 80 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Setup Time 0 0 0 ns tPWE(4) WE Pulse Width 50 55 70 ns tSD Data Setup to Write End 25 30 40 ns tHD Data Hold from Write End 0 0 0 ns tHZWE(3) WE LOW to High-Z Output 25 25 30 ns tLZWE(3) WE HIGH to Low-Z Output 5 5 5 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power) DATA-IN VALID DATA UNDEFINED tWC tSCE1 tSCE2 tAW tHA tPWE(4) tHZWE HIGH-Z tLZWE tSA tSD tHD ADDRESS CE1 CE2 WE DOUT DIN AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) |
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