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IS34C02B Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

Part # IS34C02B
Description  2K-bit 2-WIRE SERIAL CMOS EEPROM with Permanent and Reversible Write-Protection
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS34C02B Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION
Rev. 00D
03/21/06
IS34C02B
ISSI®
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS34C02B sends the initial byte sequence, the Master
device responds with an ACK indicating it requires additional
data from the IS34C02B. The IS34C02B continues to output
data for each ACK received. The Master device terminates
the sequential Read operation by pulling SDA High (no ACK)
indicating the last data byte to be read, followed by a Stop
condition.
The data output is sequential, with the data from address n
followed by the data from address n+1, ... etc. The address
counter increments by one automatically, allowing the
entire memory contents to be serially read during sequential
Read operations. When the memory address boundary 255
is reached, the address counter “rolls over” to address 0, and
the IS34C02B continues to output data for each ACK
received. (Refer to Figure 10. Sequential Read Operation
Starting with a Random Address Read Diagram.)
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/
W) bit of the Slave address is
set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
Current Address Read
The IS34C02B contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous
operation is either a Read or Write operation addressed
to the address location n, the internal address counter
would increment to address location n+1. When the
IS34C02B receives the Device Addressing Byte with a
Read operation (R/
W bit set to “1”), it will respond an ACK
and transmit the 8-bit data byte stored at address
location n+1. The Master should not acknowledge the
transfer but should generate a Stop condition so the
IS34C02B discontinues transmission. If the last byte of
the memory was the previous access, the data from
location '0' will be transmitted. (Refer to Figure 8.
Current Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and word address
of the location it wishes to read. After the IS34C02B
acknowledges the word address, the Master device resends
the Start condition and the Slave address, this time with the
R/
W bit set to one. The IS34C02B then responds with its
ACK and sends the data requested. The Master device
does not send an ACK but will generate a Stop
condition. (Refer to Figure 9. Random Address Read
Diagram.)


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