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IS42S16400D-7TLI Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS42S16400D-7TLI Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
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4 / 57 page  IS42S16400D ISSI® 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 07/05/06 PIN FUNCTIONS Symbol TSOP Pin No. Type Function (In Detail) A0-A11 23 to 26 Input Pin Address Inputs: A0-A11 are sampled during the ACTIVE 29 to 34 command (row-address A0-A11) and READ/WRITE command (A0-A7 22, 35 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. BA0, BA1 20, 21 Input Pin Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS 17 Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. CKE 37 Input Pin The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK 38 Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. CS 19 Input Pin The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQ0 to 2, 4, 5, 7, 8, 10, DQ Pin DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units DQ15 11,13, 42, 44, 45, using the LDQM and UDQM pins. 47, 48, 50, 51, 53 LDQM, 15, 39 Input Pin LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS 18 Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE 16 Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VDDQ 3, 9, 43, 49 Power Supply Pin VDDQ is the output buffer power supply. VDD 1, 14, 27 Power Supply Pin VDD is the device internal power supply. GNDQ 6, 12, 46, 52 Power Supply Pin GNDQ is the output buffer ground. GND 28, 41, 54 Power Supply Pin GND is the device internal ground. |
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