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IS61DDB42M18 Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc

Part # IS61DDB42M18
Description  36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS61DDB42M18 Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
ISSI®
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page
8.
Operation
K
(tW+1)
K
(tW+1.5)
K
(tW+2)
K
(tW+2.5)
BW0
BW1
DB
DB+1
DB+2
DB+3
Write Byte 0
L
→HL
H
D0-8 (tW+1)
Write Byte 1
L
→HH
L
D9-17 (tW+1)
Abort Write
L
→H
HH
Don’t care
Write Byte 0
L
→HL
H
D0-8 (tW+1.5)
Write Byte 1
L
→HH
L
D9-17 (tW+1.5)
Write All Bytes
L
→HL
L
D0-17 (tW+1.5)
Abort Write
L
→H
HH
Don’t care
Write Byte 0
L
→HL
H
D0-8 (tW+2)
Write Byte 1
L
→HH
L
D9-17 (tW+2)
Write All Bytes
L
→H
LL
D0-17 (tW+2)
Abort Write
L
→HH
H
Don’t care
Write Byte 0
L
→HL
H
D0-8 (tW+2.5)
Write Byte 1
L
→H
HL
D9-17 (tW+2.5)
Write All Bytes
L
→H
LL
D0-17 (tW+2.5)
Abort Write
L
→HH
H
Don’t care
Notes;
1. For all cases, R/W needs to be active low during the rising edge of K occurring at time tW
2. For timing definitions refer to the AC Characteristics on page
16. Signals must have AC specifications with respect to switching
clocks K and K.


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