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IS61LF25618A-6.5B2 Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS61LF25618A-6.5B2 Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
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4 / 25 page  4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 ISSI® IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A 119 BGA PACKAGE PIN CONFIGURATION 128K X 36 (TOP VIEW) PIN DESCRIPTIONS 123456 7 A VDDQ AA ADSP AA VDDQ B NC CE2 A ADSC A CE2 NC C NC A A VDD A A NC D DQc DQPc Vss NC Vss DQPb DQb E DQc DQc Vss CE Vss DQb DQb F VDDQ DQc Vss OE Vss DQb VDDQ G DQc DQc BWc ADV BWb DQb DQb H DQc DQc Vss GW Vss DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd Vss CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd Vss BWE Vss DQa VDDQ N DQd DQd Vss A1* Vss DQa DQa P DQd DQPd Vss A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Controls BWE Byte Write Enable Symbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply VDD Power Supply VDDQ Output Power Supply Vss Ground Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. |
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