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PPC5534AVZ40 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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PPC5534AVZ40 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 50 page  MPC5534 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Overview Freescale Semiconductor 2 PowerPC instruction set. This family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to achieve significant code size footprint reduction. The MPC5534 has a single level of memory hierarchy consisting of 64-Kbyte on-chip SRAM and 1 Mbyte of internal Flash memory. Both the SRAM and the Flash memory can hold instructions and data. The External Bus Interface has been designed to support most of the standard memories used with the MPC5xx family. The MPC5534 does not support arbitration between itself and other masters on the external bus. It must be either the only master on the external bus or act as a slave-only device. The complex I/O timer functions of the MPC5534 are performed by an Enhanced Time Processor Unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the MPC500 family’s TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of MPC5534 are performed by the enhanced Modular Timer System (eMIOS). The eMIOS 24 hardware channels are capable of single action, double action, pulse width modulation (PWM) and modulus counter operation. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including CANs, enhanced SPIs (Deserialize/Serialize Peripheral Interface) and SCIs. The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and GPIO signals. The MPC5534 MCU has an on-chip 40-channel Enhanced Queued Dual Analog-to-Digital Converter (eQADC), with 5V conversion range. The System Integration Unit (SIU) performs several chip-wide configuration functions. Pad configuration and General-Purpose Input and Output (GPIO) are controlled from the SIU. External interrupts and reset control are also found in the SIU. The Internal Multiplexer sub-block (IMUX) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing. |
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