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74F1763 Datasheet(PDF) 4 Page - NXP Semiconductors |
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74F1763 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 16 page Philips Semiconductors Product specification 74F1763 Intelligent DRAM controller (IDC) 1999 Jan 08 4 PIN DESCRIPTION SYMBOL PINS TYPE NAME AND FUNCTION SYMBOL DIP TYPE NAME AND FUNCTION REQ 48 Input Active Low Memory Access Request input, must be asserted for the entire DRAM access cycle. REQ is sampled on the rising edge of the CP clock. GNT 1 Output Active High Grant output. When High indicates that a DRAM access (inactive during refresh) cycle has begun. Asserted from the rising edge of the CP clock. PAGE 47 Input Active Low Page-Mode Access input. Forces the IDC to keep RAS asserted for as long as the PAGE input is Low and REQ is asserted Low. HLDROW 2 Input Row Address Hold input. If Low will configure the IDC to maintain the row addresses for a full CP clock cycle after RAS is asserted. If High will program the IDC to maintain row addresses for a 1/2 CP clock cycle after RAS is asserted. PRECHRG 3 Input RAS Precharge input. A Low will program the IDC to guarantee a minimum of 4 CP clock cycles of precharge. A High will guarantee 3 clock cycles of precharge. CP 46 Input Clock input. Used by the Controller for all timing and arbitration functions. RCP 45 Input Refresh Clock input. Divided internally by 64 to produce an internal Refresh Request. DTACK 6 Output Active Low, 3-state Data Transfer Acknowledge output. Enabled by the REQ input and asserted four clock cycles after the assertion of RAS, 3-stated when REQ goes High. RA0–9 44, 42, 40, 35, 33, 31, 29, 27, 25, 23 Inputs Row Address inputs. CA0–9 43, 41, 39, 34, 32, 30, 28, 26, 24, 22 Inputs Column Address inputs. Propagated to the MA0–9 outputs 1 CP clock cycle after RAS is asserted, if HLDROW = 0 or 1/2 clock cycle later if HLDROW is 1. RAS 4 Output Active Low Row Address Strobe. Asserted for four clock cycles during each refresh cycle regardless of the PAGE input. Also asserted for four clock cycles during processor access if the PAGE input is High. If PAGE is Low, RAS is negated upon negation of PAGE or REQ, whichever occurs first. CAS 5 Output Active Low Column Address Strobe. Always asserted 1.5 CP clock cycles after the assertion of RAS. Negated upon negation of REQ. HLDROW input pin does not affect RAS to CAS timing. MA0–9 7–10, 15–20 Output DRAM multiplexed address outputs. Row and column addresses asserted on these pins during an access cycle. Refresh counter addresses presented on these outputs during refresh cycles. ALE 21 Input Active Low Address Latch Enable input. A Low on this pin will cause the address latches to be transparent. A High level will latch the RA0–9 and CA0–9 inputs. VCC 36–38 +5V "10% Supply voltage. GND 11–14 Ground |
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