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IS93C66A-3PLA3 Datasheet(PDF) 3 Page - Integrated Silicon Solution, Inc |
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IS93C66A-3PLA3 Datasheet(HTML) 3 Page - Integrated Silicon Solution, Inc |
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3 / 16 page  Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. A 05/02/06 IS93C56A IS93C66A ISSI® Write All (WRALL) The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 200 ns (tCS), the DOUT pin indicates the READY/ BUSY status of the chip (see Figure 6). Vcc is required to be above 4.5V for WRALL to function properly. Write Disable (WDS) The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against acci- dental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. Erase Register (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of tCS, will cause DOUT to indicate the READ/ BUSY status of the chip: a logical “0” indicates programming is still in progress; a logical “1” indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8). Erase All (ERAL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical “1” (see Figure 9). Vcc is required to be above 4.5V for ERALL to function properly. Write Enable (WEN) The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done. When Vcc is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.) Write (WRITE) The WRITE instruction includes 8 or 16 bits of data to be written into the specified register. After the last data bit has been applied to DIN, and before the next rising edge of SK, CS must be brought LOW. If the device is write- enabled, then the falling edge of CS initiates the self- timed programming cycle (see WEN). If CS is brought HIGH, after a minimum wait of 200 ns (5V operation) after the falling edge of CS (tCS) DOUT will indicate the READY/ BUSY status of the chip. Logical “0” means programming is still in progress; logical “1” means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/ BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle, tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag. |
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