Copyright 2001-2006 THine Electronics, Inc. All rights reserved.

8

THine Electronics, Inc.

THC63LVD103 _Rev2.2

Switching Characteristics

~ +70

AC Timing Diagrams

Symbol

Parameter

Min.

Typ.

Max.

Units

CLK IN Transition time

5.0

ns

CLK IN Period

7.4

125.0

ns

CLK IN High Time

ns

CLK IN Low Time

ns

CLK IN to TCLK+/- Delay

ns

TTL Data Setup to CLK IN

2.5

ns

TTL Data Hold from CKL IN

0

ns

LVDS Transition Time

0.6

1.5

ns

Output Data Position0

-0.2

0.0

+0.2

ns

Output Data Position1

ns

Output Data Position2

ns

Output Data Position3

ns

Output Data Position4

ns

Output Data Position5

ns

Output Data Position6

ns

Phase Lock Loop Set

10.0

ms

°C

°C

t

TCP

7

-----------0.2

–

t

TCP

7

-----------

t

TCP

7

-----------0.2

+

2

t

TCP

7

-----------0.2

–2

t

TCP

7

-----------2

t

TCP

7

-----------0.2

+

3

t

TCP

7

-----------0.2

–3

t

TCP

7

-----------3

t

TCP

7

-----------0.2

+

4

t

TCP

7

-----------0.2

–4

t

TCP

7

-----------4

t

TCP

7

-----------0.2

+

5

t

TCP

7

-----------0.2

–5

t

TCP

7

-----------5

t

TCP

7

-----------0.2

+

6

t

TCP

7

-----------0.2

–6

t

TCP

7

-----------6

t

TCP

7

-----------0.2

+

TTL Input

5pF

20%

80%

20%

80%

CLK IN

LVDS Output

90%

10%

90%

10%

100

Ω

TA+

TA-

LVDS Output Load