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TPS54317 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS54317 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 17 page www.ti.com LAYOUT CONSIDERATIONS FOR THERMAL PIN 1 0.1250 0.0120 24 x 0.0320 24 x 0.1182 0.0197 0.1620 0.0400 0.0400 6 x 0.013 DIA EXPOSED POWERPAD AREA TPS54317 SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006 operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias PERFORMANCE to avoid solder wicking through the vias. Six vias For operation at full rated load current, the analog should be in the PowerPAD area additional vias ground plane must provide adequate heat dissipating located under the device package may be added to area. A 3 inch by 3 inch plane of 1 ounce copper is enhance thermal performance. The vias under the recommended, though not mandatory, depending on package, but not in the exposed thermal pad area, ambient temperature and airflow. Most applications can be increased in size to 0.018. have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater Figure 12. Recommended Land Pattern for 24-Pin QFN PowerPAD 10 Submit Documentation Feedback |
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