February 2002

Rev. 0

W3DG6430V-D2

5

White Electronic Designs

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

PRELIMINARY

AC CHARACTERISTICS

133MHz component timing

Paramater

Symbol

Min

Max

Units

Notes

Access time from CLK

CL = 2

5.4

ns

Address hold time

0.8

ns

Address setup time

1.5

ns

CLK high level width

2.5

ns

CLK low level width

2.5

ns

Clock cycle time

CL = 2

7.5

ns

1

CKE hold time

0.8

ns

CKE setup time

1.5

ns

CS, RAS, CAS, WE, DQM hold time

0.8

ns

CS, RAS, CAS, WE, DQM setup time

1.5

ns

Data-in hold time

0.8

ns

Data-in setup time

1.5

ns

Data-out high-impedance time

CL = 2

5.4

ns

2

Data-out low-impedance time

1ns

Data-out hold time (load)

3ns

Data-out hold time (no load)

1.8

ns

3

Active to Precharge command

37

120,000

ns

Active to Active command period

60

ns

Active to Read or Write delay

15

ns

Refresh period

64

ms

Auot refresh period

66

ns

Precharge command period

15

ns

Active bank a to Active bank b command

14

ns

Transition time

0.3

1.2

ns

4

Write recovery time

1 CLK + 7ns

ns

5

ns

6

Exit Self Refresh to Active command

67

ns

7

Notes:

1. The clock frequency must remain constant ( stable clock is defined as a signal cycling within

timing constraints specified for the clock pin) during access or precharge states (READ,

WRITE, including WR and Precharge commands). CKE may be used to reduce the data rate.

3. Paramater guaranteed by design

delay, after the last Write is executed.

6. Precharge mode only.

7. CLK must be toggled a minimum of two times during this period.

MODULE AC CHARACTERISTIC

Symbol

Min

Max

Units

Notes

Address hold time

AH

0

ns

Address setup time

AS

4.5

ns

CS, RAS, CAS, WE, DQM hold time

CMH

0

ns

CS, RAS, CAS, WE, DQM setup time

CMS

4.5

ns