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W3E32M64S-333BM Datasheet(PDF) 10 Page - White Electronic Designs Corporation |
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W3E32M64S-333BM Datasheet(HTML) 10 Page - White Electronic Designs Corporation |
10 / 17 page W3E32M64S-XBX 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior ABSOLUTE MAXIMUM RATINGS Parameter Unit Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 V Voltage on I/O pins relative to VSS -1 to 3.6 V Operating Temperature TA (Mil) -55 to +125 °C Operating Temperature TA (Ind) -40 to +85 °C Storage Temperature, Plastic -55 to +125 °C NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (NOTE 13) Parameter Symbol Max Unit Input Capacitance: CLK CI1 8 pF Addresses, BA0-1 Input Capacitance CA 22 pF Input Capacitance: All other input-only pins CI2 10 pF Input/Output Capacitance: I/Os CIO 10 pF BGA THERMAL RESISTANCE Description Symbol Max Units Notes Junction to Ambient (No Airflow) Theta JA 14.1 °C/W 1 Junction to Ball Theta JB 10.0 °C/W 1 Junction to Case (Top) Theta JC 5.2 °C/W 1 NOTE 1: Refer to "PBGA Thermal Resistance Correlation" Application Note at www.wedc.com in the application notes section for modeling conditions. to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR, because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. * Self refresh available in commercial and industrial temperatures only. |
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