W3E32M72SR-XSBX

2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

July 2006

Rev. 3

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

DENSITY COMPARISONS

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed. The address bits registered

coincident with the READ or WRITE command are used

to select the bank and the starting column location for the

burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, or 8 locations. An auto

precharge function may be enabled to provide a self-

timed row precharge that is initiated at the end of the

burst access.

The pipelined, multibank architecture of DDR SDRAMs allows

for concurrent operation, thereby providing high effective

bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-

saving power-down mode. All inputs are compatible with

the Jedec Standard for SSTL_2. All full drive options

outputs are SSTL_2, Class II compatible.

FUNCTIONAL DESCRIPTION

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank and

row to be accessed (BA0 and BA1 select the bank, A0-12

select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be

initialized. The following sections provide detailed

information covering device initialization, register definition,

command descriptions and device operation.

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than

those specified may result in undefined operation. Power

16

25

66

TSOP

66

TSOP

66

TSOP

66

TSOP

66

TSOP

11.9

11.9

11.9

22.3

Monolithic Solution

Actual Size

S

A

V

I

N

G

S

Area

I/O

Count

5 x 66 pins + 2 x 48 = 426 pins

74%

208 Balls

51%

W3E32M72SR-XSBX

White Electronic Designs

48

TSOP

12.6

48

TSOP

12.6

8.3

11.9

22.3

22.3