W3E32M72S-XSBX

8

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

July 2006

Rev. 6

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

COMMAND

READ

NOP

NOP

NOP

CL = 2.5

DON'T CARE

TRANSITIONING DATA

DQ

DQS

T0

T1

T2

T2n

T3

T3n

COMMAND

READ

NOP

NOP

NOP

CL = 2

DQ

DQS

CLK

CLK

T0

T1

T2

T2n

T3

T3n

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

DATA

CLK

CLK

FIG. 4 CAS LATENCY

FIG. 5 EXTENDED MODE REGISTER

DEFINITION

DLL

Enable

Disable

Extended Mode

Register (Ex)

Address Bus

Operating Mode

11

01

E0

0

1

Drive Strength

Normal

Reduced

E1

0

1

Operating Mode

Reserved

Reserved

E1, E0

Valid

-

E12

0

-

E10

0

-

E9

0

-

E8

0

-

E7

0

-

E6

0

-

E5

0

-

E4

0

-

E3

0

-

E11

0

-

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)

2. The QFC# function is not supported.

E2

0

-

14 13 12 11 10

9

8

76543210

DLL

DS

must be activated prior to any READ or WRITE commands

being issued to that bank. A PRECHARGE command will

be treated as a NOP if there is no open row in that bank

(idle state), or if the previously open row is already in the

process of precharging.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the

same individual-bank PRECHARGE function described

above, but without requiring an explicit command. This is

accomplished by using A10 to enable AUTO PRECHARGE

in conjunction with a specific READ or WRITE command.

A precharge of the bank/row that is addressed with the

READ or WRITE command is automatically performed

upon completion of the READ or WRITE burst. AUTO

PRECHARGE is nonpersistent in that it is either enabled

or disabled for each individual READ or WRITE command.

The device supports concurrent auto precharge if the

command to the other bank does not interrupt the data

transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is

initiated at the earliest valid stage within a burst. This

“earliest valid stage” is determined as if an explicit

precharge command was issued at the earliest possible

another command to the same bank until the precharge

BURST TERMINATE

The BURST TERMINATE command is used to truncate

READ bursts (with auto precharge disabled). The most

recently registered READ command prior to the BURST

TERMINATE command will be truncated. The open page

which the READ burst was terminated from remains

open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the

DDR SDRAM and is analogous to CAS-BEFORE-RAS

(CBR) REFRESH in conventional DRAMs. This command

is nonpersistent, so it must be issued each time a refresh

is required. All banks must be idle before an AUTO

REFRESH command is issued.

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”