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W3EG264M64ETSRXXXJD3MG Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3EG264M64ETSRXXXJD3MG Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
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6 / 13 page  6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs April 2005 Rev. 0 W3EG264M64ETSR-JD3 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes PLL and register power Parameter Symbol Conditions DDR333@ CL=2.5 Max DDR266@ CL=2 Max DDR266@ CL=2.5 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 2480 2480 2480 mA Operating Current IDD1 One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 2720 2720 2720 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 80 80 80 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 1030 1030 1030 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 560 560 560 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active- Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 1110 1110 1110 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 2760 2760 2760 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 2840 2840 2840 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 3740 3740 3740 mA Self Refresh Current IDD6 CKE ≤ 0.2V 410 410 410 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 4680 4680 4680 mA |
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