W3E232M16S-XSTX

9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

December 2005

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

PRELIMINARY*

FIGURE 5 – EXTENDED MODE REGISTER

DEFINITION

DLL

Enable

Disable

Extended Mode

Register (Ex)

Address Bus

Operating Mode

11

01

E0

0

1

Drive Strength

Normal

Reduced

E1

0

1

Operating Mode

Reserved

Reserved

E1, E0

Valid

-

E12

0

-

E10

0

-

E9

0

-

E8

0

-

E7

0

-

E6

0

-

E5

0

-

E4

0

-

E3

0

-

E11

0

-

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)

2. The QFC# function is not supported.

E2

0

-

14 13 12 11 10

9

8

76543210

DLL

DS

BURST TERMINATE

The BURST TERMINATE command is used to truncate

READ bursts (with auto precharge disabled). The most

recently registered READ command prior to the BURST

TERMINATE command will be truncated. The open page

which the READ burst was terminated from remains

open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the

DDR SDRAM and is analogous to CAS-BEFORE-RAS

(CBR) REFRESH in conventional DRAMs. This command

is nonpersistent, so it must be issued each time a refresh

is required. All banks must be idle before an AUTO

REFRESH command is issued.

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”

TRUTH TABLE – COMMANDS (NOTE 1)

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

DESELECT (NOP) (9)

H

X

X

X

X

NO OPERATION (NOP) (9)

L

H

H

H

X

ACTIVE (Select bank and activate row) ( 3)

L

L

H

H

Bank/Row

READ (Select bank and column, and start READ burst) (4)

L

H

L

H

Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4)

L

H

L

L

Bank/Col

BURST TERMINATE (8)

L

H

H

L

X

PRECHARGE (Deactivate row in bank or banks) ( 5)

L

L

H

L

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

L

L

L

H

X

LOAD MODE REGISTER (2)

L

L

L

L

Op-Code

NOTES:

1.

CKE is HIGH for all commands shown except SELF REFRESH.

2.

A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1

select either the mode register (0, 0) or the extended mode register (1, 0).

3.

A0-12 provide row address, and BA0, BA1 provide bank address.

4.

A0-9 provide column address; A10 HIGH enables the auto precharge feature (non

persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide

bank address.

5.

A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks

precharged and BA0, BA1 are “Don’t Care.”

6.

This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is

LOW.

7.

Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t

Care” except for CKE.

8.

Applies only to read bursts with auto precharge disabled; this command is

undefined (and should not be used) for READ bursts with auto precharge enabled

and for WRITE bursts.

9.

DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.