W3E232M16S-XSTX

4

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

December 2005

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

PRELIMINARY*

bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-

saving power-down mode. All inputs are compatible with

the Jedec Standard for SSTL_2. All full drive options

outputs are SSTL_2, Class II compatible.

FUNCTIONAL DESCRIPTION

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank and

row to be accessed (BA0 and BA1 select the bank, A0-12

select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be

initialized. The following sections provide detailed

information covering device initialization, register definition,

command descriptions and device operation.

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than

those specified may result in undefined operation. Power

valid until after VREF is applied. CKE is an SSTL_2 input

SSTL_2 signal and remain as such until power is cycled.

Maintaining an LVCMOS LOW level on CKE during power-

up is required to ensure that the DQ and DQS outputs will

be in the High-Z state, where they will remain until driven

in normal operation (by a read access). After all power

supply and reference voltages are stable, and the clock

is stable, the DDR SDRAM requires a 200µs delay prior

to applying an executable command.

Once the 200µs delay has been satisfied, a DESELECT

or NOP command should be applied, and CKE should

GENERAL DESCRIPTION

The 2x32Mx16 (1Gb) DDR SDRAM is a high-speed CMOS,

dynamic random-access, memory using 2 chips containing

536,870,912 bits. Each chip is internally configured as a

quad-bank DRAM.

The 2x32Mx16 DDR SDRAM uses a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access for the 2x32Mx16 DDR SDRAM effectively consists

of a single 2n-bit wide, one-clock-cycle data tansfer at the

internal DRAM core and two corresponding n-bit wide,

one-half-clock-cycle data transfers at the I/O pins.

A bi-directional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver.

strobe transmitted by the DDR SDRAM during READs and

by the memory contoller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data

for WRITEs. Each chip has two data strobes, one for the

lower byte and one for the upper byte.

The 2x32Mx16 DDR SDRAM operates from a differential

clock (CK and CK#); the crossing of CK going HIGH and

CK# going LOW will be referred to as the positive edge of

CK. Commands (address and control signals) are registered

at every positive edge of CK. Input data is registered on

both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.Read and

write accesses to the DDR SDRAM are burst oriented;

accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed. The address bits registered

coincident with the READ or WRITE command are used

to select the bank and the starting column location for the

burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, or 8 locations. An auto

precharge function may be enabled to provide a self-

timed row precharge that is initiated at the end of the

burst access.

The pipelined, multibank architecture of DDR SDRAMs allows

for concurrent operation, thereby providing high effective