Electronic Components Datasheet Search |
|
W3E64M72S-250BI Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
|
W3E64M72S-250BI Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 19 page W3E64M72S-XBX ADVANCED* 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 White Electronic Designs Corp. reserves the right to change products or specifications without notice. 64Mx72 DDR SDRAM FEATURES Data rate = 200, 250, 266 and 333Mbs Package: • 219 Plastic Ball Grid Array (PBGA), 25 x 32mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; center- aligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRanges Organized as 64M x 72 Weight: W3E64M72S-XBX - 4.5 grams typical * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. BENEFITS 66% Space Savings vs. TSOP Reduced part count 55% I/O reduction vs TSOP Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match GENERAL DESCRIPTION The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 9 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 512MB DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 512MB DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. |
Similar Part No. - W3E64M72S-250BI |
|
Similar Description - W3E64M72S-250BI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |