W3EG128M72ETSU202JD3 datasheet(5/14 Pages) WEDC

Part #	W3EG128M72ETSU202JD3

Description	1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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5 / 14 page

W3EG128M72ETSU-D3

-JD3

-AJD3

5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

January 2005

Rev. 0

ADVANCED

IDD SPECIFICATIONS AND TEST CONDITIONS

0°C

≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V ± 0.1V (200MHz)

Parameter

Symbol

Conditions

DDR400@

CL=3

DDR333@

CL=2.5

DDR266@

CL=2, 2.5

DDR200@

CL=2

Units

Max

Operating Current

IDD0

One device bank; Active - Precharge;

(MIN); DQ,DM and DQS inputs

changing once per clock cycle;

Address and control inputs changing

once every two cycles. TRC=TRC(MIN);

TCK=TCK

TBD

mA

Operating Current

IDD1

One device bank; Active-

Read-Precharge; Burst = 2;

TRC=TRC(MIN);TCK=TCK (MIN); Iout

= 0mA; Address and control inputs

changing once per clock cycle.

TBD

mA

Precharge Power-

Down Standby

Current

IDD2P

All device banks idle; Power-down

mode; TCK=TCK(MIN); CKE=(low)

TBD

mA

Idle Standby Current

IDD2F

CS# = High; All device banks idle;

TCK=TCK(MIN); CKE = high; Address

and other control inputs changing once

per clock cycle. VIN = VREF for DQ,

DQS and DM.

TBD

mA

Active Power-Down

Standby Current

IDD3P

One device bank active; Power-down

mode; TCK(MIN); CKE=(low)

TBD

mA

Active Standby

Current

IDD3N

CS# = High; CKE = High; One

device bank; Active-Precharge;

TRC=TRAS(MAX); TCK=TCK(MIN); DQ,

DM and DQS inputs changing twice

per clock cycle; Address and other

control inputs changing once per clock

cycle.

TBD

mA

Operating Current

IDD4R

Burst = 2; Reads; Continous burst;

One device bank active;Address

andcontrol inputs changing once

per clock cycle; TCK=TCK(MIN); IOUT

= 0mA.

TBD

mA

Operating Current

IDD4W

Burst = 2; Writes; Continous burst;

One device bank active; Address and

control inputs changing once per clock

cycle; TCK=TCK(MIN); DQ,DM and

DQS inputs changing twice per clock

cycle.

TBD

mA

Auto Refresh Current

IDD5

TRC=TRC(MIN)

TBD

mA

Self Refresh Current

IDD6

CKE ≤ 0.2V

TBD

mA

Operating Current

IDD7A

Four bank interleaving Reads (BL=4)

with auto precharge with TRC=TRC

(MIN); TCK=TCK(MIN); Address and

control inputs change only during

Active Read or Write commands

TBD

mA

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