W3E64M72S-XBX

9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

June 2005

Rev. 0

ADVANCED

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

COMMAND

READ

NOP

NOP

NOP

CL = 2.5

DON'T CARE

TRANSITIONING DATA

DQ

DQS

T0

T1

T2

T2n

T3

T3n

COMMAND

READ

NOP

NOP

NOP

CL = 2

DQ

DQS

CLK

CLK#

T0

T1

T2

T2n

T3

T3n

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

DATA

CLK

CLK#

FIGURE 4 – CAS LATENCY

FIGURE 5 – EXTENDED MODE REGISTER

DEFINITION

DLL

Enable

Disable

Extended Mode

Register (Ex)

Address Bus

11

01

E0

0

1

Drive Strength

Normal

Reserved

E1

0

1

Operating Mode

Reserved

Reserved

E1, E0

Valid

-

E12

0

-

E10

0

-

E9

0

-

E8

0

-

E7

0

-

E6

0

-

E5

0

-

E4

0

-

E3

0

-

E11

0

-

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)

2. The QFC# function is not supported.

E2

0

-

14 13 12 11 10

9

8

76543210

DLL

DS

Operating Mode

during an AUTO REFRESH command. Each DDR SDRAM

requires AUTO REFRESH cycles at an average interval

of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the absolute

refresh interval is provided. A maximum of eight AUTO

REFRESH commands can be posted to any given DDR

SDRAM, meaning that the maximum absolute interval

between any AUTO REFRESH command and the next

AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This

maximum absolute interval is to allow future support for

DLL updates internal to the DDR SDRAM to be restricted

to AUTO REFRESH cycles, without allowing excessive

Although not a JEDEC requirement, to provide for future

functionality features, CKE must be active (High) during

the AUTO REFRESH period. The AUTO REFRESH period

begins when the AUTO REFRESH command is registered

SELF REFRESH*

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the DDR

SDRAM retains data without external clocking. The SELF

REFRESH command is initiated like an AUTO REFRESH

command except CKE is disabled (LOW). The DLL is

automatically disabled upon entering SELF REFRESH and

is automatically enabled upon exiting SELF REFRESH (A

DLL reset and 200 clock cycles must then occur before a

READ command can be issued). Input signals except CKE

are “Don’t Care” during SELF REFRESH. VREF voltage is

also required for the full duration of SELF REFRESH.

The procedure for exiting self refresh requires a sequence

of commands. First, CK and CK# must be stable prior

to CKE going back HIGH. Once CKE is HIGH, the DDR

because time is required for the completion of any internal

refresh in progress.

A simple algorithm for meeting both refresh and DLL

Reset and NOPs for 200 additional clock cycles before

applying any other command.

* Self refresh available in commercial and industrial temperatures only.