White Electronic Designs

W3EG6462S-D3

-JD3

10

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

May 2005

Rev. 4

ADVANCED

test load. In practice, the voltage levels obtained from a properly terminated bus will

provide significantly different voltage values.

pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.

supply and the input pin.

DDR SDRAM at 100 MHz.

40. The current part operates below the slowest JEDEC operating frequency of

83 MHz. As such, future die may not reflect this option.

41. Random addressing changing and 50 percent of data changing at every transfer.

42. Random addressing changing and 100 percent of data changing at every transfer.

43. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be

45. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles.

46. Leakage number reflects the worst case leakage possible through the module pin,

not what each memory device contributes.

47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or

logic LOW.

120,000ns at any slower frequency.