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W3EG7264S335AD4 Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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W3EG7264S335AD4 Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 13 page White Electronic Designs 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com January 2005 Rev. 3 W3EG7264S-AD4 -BD4 PRELIMINARY* 512MB – 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL Double-data-rate architecture DDR200, DDR266 DDR333 • JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.2V 200 pin SO-DIMM package • Package height options: AD4: 35.05 mm (1.38”) BD4: 31.75 mm (1.25”) NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option The W3EG7264S is a 2x32Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of nine 64Mx8 DDR SDRAMs stacked in 54 pin TSOP packages mounted on a 200 pin FR4 substrate. This module is structured as 2 Ranks of 64Mx72 DDR SDRAM. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION FEATURES OPERATING FREQUENCIES DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2 Clock Speed 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2.5-3-3 2-2-2 |
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