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W3EG7234S202JD3 Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3EG7234S202JD3 Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 14 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG7234S-D3 -JD3 -AJD3 December 2004 Rev. 2 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM components only Parameter Symbol Rank 1 Conditions DDR266@CL=2 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1935 1800 1800 mA Operating Current IDD1 One device bank; Active-Read-Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 2115 1935 1935 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low) 54 54 54 mA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 810 720 720 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE = (low) 450 360 360 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 900 810 810 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA. 2160 2025 2025 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 2115 1980 1980 mA Auto Refresh Current IDD5 tRC = tRC (MIN) 3150 3060 3060 mA Self Refresh Current IDD6 CKE ≤ 0.2V 54 36 36 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. 4275 4185 4185 mA |
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