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W3EG7264S263JD3 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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W3EG7264S263JD3 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
5 / 11 page 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2005 Rev. 5 W3EG7264S-JD3-D3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V Includes DDR SDRAM component only Parameter Symbol Conditions DDR400@ CL=3 Max DDR333@ CL=2.5 Max DDR266@ CL=2 Max DDR266@ CL=2.5 Max DDR200@ CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1395 1170 1170 1170 1170 mA Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 1665 1440 1440 1440 1440 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 45 45 45 45 45 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 495 405 405 405 405 mA Active Power-Down Standby Current IDD3P One device bank active; Power- Down mode; tCK (MIN); CKE=(low) 405 315 315 315 315 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 540 450 450 450 450 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 1710 1485 1485 1485 1485 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 1758 1575 1575 1575 1575 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 3105 2610 2610 2610 2610 mA Self Refresh Current IDD6 CKE ≤ 0.2V 45 45 45 45 45 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 4050 3645 3645 3645 3645 mA |
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