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W3EG72128S265AD4-XG Datasheet(PDF) 7 Page - White Electronic Designs Corporation

Part # W3EG72128S265AD4-XG
Description  1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

W3EG72128S265AD4-XG Datasheet(HTML) 7 Page - White Electronic Designs Corporation

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG72128S-AD4
-BD4
August 2005
Rev. 3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
-0.75
+0.75
-0.75
0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
7.5
13
7.5
13
ns
39, 44
CL = 2
tCK (2)
7.5
13
7.5
13
7.5/10
13
ns
39, 44
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
1.75
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
0.4
0.5
0.5
ns
22, 23
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.20
0.20
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.20
0.20
0.2
tCK
Half clock period
tHP
tCH,tCL
tCH,tCL
tCH, tCL
ns
30
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
+0.75
ns
16, 36
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.75
-0.75
ns
16, 36
Address and control input hold time (fast slew rate)
tIHF
0.75
0.90
0.90
ns
12
Address and control input setup time (fast slew rate)
tISF
0.75
0.90
0.90
ns
12
Address and control input hold time (slow slew rate)
tIHS
0.8
1
1
ns
12


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