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W3HG128M64EEUXXXD4SG Datasheet(PDF) 10 Page - White Electronic Designs Corporation |
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W3HG128M64EEUXXXD4SG Datasheet(HTML) 10 Page - White Electronic Designs Corporation |
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10 / 14 page  W3HG128M64EEU-D4 March 2006 Rev. 0 ADVANCED* 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Notes: 1. All voltages referenced to VSS. 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference / supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is disabled for all measurements that are not ODT-specific. 3. Outputs measured with equivalent load: 4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.0V in the test environment and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as specified. 5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. There are two sets of values listed for Command/Address: tISa, tIHa and tISb, tIHb. The tISa, tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb at VREF when the slew rate is 1V/ns. The baseline values, tISb, tIHb, are the JEDEC defined values, referenced from the logic trip points. tISb is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal, while tIHb is referenced from VIL (DC) for a rising signal and VIH (DC) for a falling signal. If the Command/Address slew rate is not equal to 1 V/ns, then the baseline values must be derated. 7. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: tDSa. tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference only) are equivalent to the baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic trip points. tDSb is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal, while tDSb is referenced from VIL (DC) for a rising signal and VIH (DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated. If the DQS differential strobe feature is not enabled, then the DQS strobe is single-ended, the baseline values not applicable, and timing is not referenced to the logic trip points. Single- ended DQS data timing is referenced to DQS crossing VREF. 8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 9. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 10. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition 11. The intent of the "Don’t Care" state after completion of the postamble is the DQS- driven signal should either be high, low or High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above VIHDC(min) then it must not transition low (below VIH(DC) prior to tDQSH(min). 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to an average refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial). However, a REFRESH command must be asserted at least once every 70.3µs or tRFC (MAX). To ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands must be issued every 64ms. 15. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15. 16. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially). 17. The data valid window is derived by achieving other specifications - tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. READs and WRITEs with auto precharge are allowed to be issued before tRAS(MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM. 19. VIL/VIH DDR2 overshoot/undershoot. 20. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be rounded up to the next integer. tCK refers to the application clock period; nWR refers with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks. 21. The minimum internal READ to PRECHARGE time. This is the time from the last 4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the READ so that data will output CL later. This parameter is only applicable when tRTP/(2x tCK) > 1, such as frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/ (2x tCK) ≤ 1, then equation AL + BL/2 applies. tRAS (MIN) also has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. 22. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; AC Operation Condition Notes: nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For -533Mb/s at tCK = 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. 24. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high-Z. Both are measured from tAOFD. 25. This parameter has a two clock minimum requirement at any tCK. 26. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. 27. tISXR is equal to tIS and is used for CKE setup time during self refresh exit. 28. No more than 4 bank ACTIVE commands may be issued in a given tFAW(min) period. tRRD(min) restriction still applies. The tFAW(min) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. 29. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA(MIN) applies to all 8-bank DDR2 devices. 30. Value is minimum pulse width, not the number of clock registrations. 31. This is applicable to Read cycles only. Write cycles generally require additional time due to tWR during auto precharge. 32. tCKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 33. This parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving (tRPST) or beginning to drive (tRPRE). 34. When DQS is used single-ended, the minimum limit is reduced by 100ps. 35. The half-clock of tAOFD's 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47 for tAOF (MIN) and 2.5 + 0.03 or 2.53 for tAOF (MAX). 36. The clock’s tCKAVG is the average clock over any 200 consecutive clocks and Output (VOUT) Reference Point 25Ω VTT = VCCQ/2 |
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