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W3H64M72E-SBM Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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W3H64M72E-SBM Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 30 page W3H64M72E-XSBX ADVANCED* 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs March 2006 Rev. 1 White Electronic Designs Corp. reserves the right to change products or specifications without notice. 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Package: • 208 Plastic Ball Grid Array (PBGA), 17 x 23mm • 1.0mm pitch DDR2 Data Rate = 667*, 533, 400 Core Supply Voltage = 1.8V ± 0.1V I/O Supply Voltage = 1.8V ± 0.1V - (SSTL_18 compatible) Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable data – output drive strength Programmable CAS latency: 3, 4 or 5 Posted CAS additive latency: 0, 1, 2, 3 or 4 Write latency = Read latency - 1* tCK Commercial, Industrial and Military Temperature Ranges Organized as 64M x 72 Weight: W3H64M72E-XSBX - 2.5 grams typical BENEFITS 63% SPACE SAVINGS vs. FPBGA Reduced part count 55% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 128M x 72 density (contact factory for information) * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. Area 5 x 209mm2 = 1,045mm2 391mm2 63% 5 x 92 balls = 460 balls 208 Balls 55% S A V I N G S I/O Count Actual Size W3H64M72E-XSBX CSP Approach (mm) 90 FBGA 11.0 19.0 23 17 90 FBGA 11.0 90 FBGA 11.0 90 FBGA 11.0 90 FBGA 11.0 FIGURE 1 – DENSITY COMPARISONS White Electronic Designs W3H64M72E-XSBX |
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